Hello, dear friend, you can consult us at any time if you have any questions, add WeChat: daixieit

ELEN30010 Digital System Design

End of Semester 1 2019

Question 1.1 (10 marks)

Write down the truth table for a Full Adder (as in Workshop 2).

Question 1.2 (10 marks)

Write a Verilog module implementing a Full Adder. Use a case statement. When defining numbers, make sure to state explicitly their size (number of bits).

Question 2.1 (10 marks)

Draw the state diagram for a Moore FSM that implements an edge detector (as in Workshop 4). Recall that the input to the edge detector is a sequence of bits, and we wish to detect       transitions, both low to high and high to low. For example, an input sequence of 0011110      should produce the output sequence 0010001. You should give the states meaningful             names (or meaningful numerical values). Clearly identify the starting state, based on the        requirements that the initial output is 0 and if the very first input bit is a 0 then the                 corresponding output should be 0 (no edge detected).

Question 2.2 (10 marks)

Write a Verilog module implementing an edge detector. Write it as a Moore FSM in canonical form. (You do not need to use localparam if your states have meaningful numerical values.) Explicitly include the size (number of bits) of each number.

Question 3 (10 marks)

In the Workshops, we used a parametrised module called Synchroniser where the                   parameter n denotes the width (number of bits) of the input. The module synchronises each bit of its input by putting it through a double flip-flop synchroniser. Write the Verilog code    for this Synchroniser. The first two lines are given below for you.

module Synchroniser(clk, in, out);

parameter n = 1;

Question 4.1 (4+6 = 10 marks)

In Workshop 6 we assigned “don’t know” to certain bits of certain registers.

A/ Will this cause the output of a flip-flop inside the FPGA to take on the don’t know value “x” (and not a 0 or a 1)? Briefly explain and justify your answer.

B/ Briefly explain why we assigned certain bits to don’t know” rather than to 0.

Question 4.2 (3+2+3+2 = 10 marks)

In Workshop 6 we introduced several new Verilog expressions.

a) Explain precisely what $clog2 does and why we use it.

b) What does $clog2(9) equal? Show how you arrived at this answer.

c) Explain precisely what the notation x[3 +: 2] means.

d) If x = 8’b0100_1101 then what does x[3 +: 2] equal? Show how you arrived at this answer. (You may assume x is declared as reg [7:0] x;)

Question 5 (15 marks)

Write down exactly what the following Verilog code will output.

module Test;

reg [3:0] x;

reg signed [3:0] y;

reg [7:0] z;

reg signed [7:0] t;

initial begin

x = 5;

y = 12;

z = x+y;

t = 5+y;

$display("a/ %b", x);

$display("b/ %b", y);

$display("c/ %b", z);

$display("d/ %b", t);

$display("e/ ", x);

$display("f/ ", y);

$display("g/ ", z);

$display("h/ ", t);

z = 8'hca;

$display("i/ %b", z);

$display("j/ ", z);

$display("k/ %b", !z);

$display("l/ %b", ~z);

$display("m/ %b", &z);

$display("n/ %b", |z);

end

endmodule

Question 6 (10 marks)

Draw the circuit diagram of a CMOS OR gate (two inputs and one output) using only n-          channel and p-channel FETs. Use standard circuit symbols for the FETs, clearly distinguishing between n-channel and p-channel FETs. Label the gate, source and drain of each FET.

Question 7 (2+4+4 = 10 marks)

a) In Verilog, the behaviour of a real logic gate can be modelled by an ideal logic gate followed by a delay. What is the best type of delay to use in this model? Why?

b) An inverter can be made from an n-channel and a p-channel FET. Explain why such an inverter swallows short pulses. (Give your answer in terms of the simple model of a FET discussed in lectures.)

c) Explain why logic gates have propagation delays. (Give your answer in terms of the simple model of a FET discussed in lectures.)

Question 8 (3+2+3+2 = 10 marks)

In a shared bus arrangement, it is important that each device connected to the bus can be put in a high-impedance state.

A/ What is a high-impedance state? And how is it denoted in Verilog?

B/ Why is it important that devices using a shared bus can be put into a high-impedance state?

C/ What are two advantages of a shared bus over direct connections between every pair of devices?

D/ What is a disadvantage of a shared bus over direct connections between every pair of devices?

Question 9 (10 marks)

Draw the circuit diagram (using standard logic gate symbols) for the following combinational circuit. (Do not optimise the circuit; draw it in a way which corresponds best with its Verilog description.)

module DrawMe(input a, b, c, output e);

assign e = ((a & b) | !(b & c)) ^ (a & c);

endmodule

Question 10 (15 marks)

The questions below are all True or False questions. You have three options. Write the          whole word TRUE, write the whole word FALSE, or leave the answer blank. You will receive 1 mark for the correct answer; you will lose 2 marks for the wrong answer; and you will        receive 0 marks if you leave the answer blank. If there is any ambiguity in your answer, it     will be taken as being the wrong answer. If your final score is negative, it will be made zero.

1/ The Cyclone V FPGA contains a 50 MHz clock.

2/ The Cyclone V FPGA contains D Latches and Look-up Tables (LUTs).

3/ The Cyclone V FPGA runs Verilog code.

4/ One-hot encoding requires the least number of flip-flops.

5/ FETs are a type of transistor.

6/ A good FET for digital logic should have a very large resistance when in the ON state and a very small capacitance.

7/ Metastability is unavoidable in a Finite-State Machine operating within a single clock domain.

8/ Metastability is unavoidable when crossing clock domains.

9/ All syntactically-correct Verilog code can be simulated.

10/ Every Moore Finite-State Machine is also a Mealy Finite-State Machine.

11/ Verilog was designed for synthesising digital logic.

12/ FIFO stands for Flip-flop In, Flip-flop Out.

13/ Functional simulations cannot detect timing errors.

14/ An inertial delay of 2 ns will swallow all pulses less than or equal to 2 ns in duration.

15/ Quartus’ RTL viewer shows which LUTs will be used in the FPGA.