Question 1.1 (12 marks)

Draw the state transition diagram for the following Moore Finite-State Machine (FSM). Use only five states. Give the states meaningful names (not numbers).

The FSM has 3 output bits, labelled R, G and B. (You can think of these as connected to three LEDs, a Red, a Green and a Blue LED.)

The FSM has 2 input bits, with the following meaning.

00 – the output is 000 (all LEDs off).

01 – the output cycles repeatedly, first 100 then 010 then 001, then back to 100 then 010 then 001 and so forth (the LEDs will repeatedly light up in the order red then green then blue).

10 – the output cycles repeatedly in the opposite direction: first 001 then 010 then 100, then back to the beginning, so 001 then 010 then 100 again, and so forth (the LEDs will repeatedly light up in the  order blue then green then red).

11 – the output is 111 (all LEDs on).

Question 1.2 (12 marks)

Implement in Verilog the FSM in Question 1.1, in canonical form (as taught in lectures). Use            localparam to give numbers to the states, using the naming convention you chose in your answer to Question 1.1. Explicitly initialise the FSM to the state having the output of 3’b000. Use exactly the   following module definition: module MyFSM(input clk, input [1:0] in, output [2:0] out);

Use assign statements to determine each bit of the output, as in: assign out[0] = …; assign out[1] = …; assign out[2] = …;

Use casex({state,in}) for the transition logic.

Question 2 (9 marks)

Write down the output of the following Verilog code.

module Jiayou;

initial #10 $display("Hello!");

reg clk = 0;

initial repeat (12) #1 clk = !clk;

reg signed [3:0] x = 0;

always @(posedge clk) begin

x <= x + 3;

$display("Time = %2d, x = %2d", $time, x);

end

endmodule

Question 3 (15 marks)

Draw the timing diagram for the following combinational circuit. Assume all rise and fall times are  infinitely fast. However, the inverters have a contamination delay of 1 unit and a propagation delay of 2 units. The XOR gate has a contamination delay of 2 units and a propagation delay of 3 units.    Assume the input (labelled“a”) has been 0 for a long time before the input sketched below is        applied. (Note: this is not a useful circuit!)

b

For Working Out Only

(Answer goes in the above wave diagram.)

Question 4 (6 marks)

Draw the circuit diagram (using standard logic gate symbols) for the following combinational circuit. (Do not optimise the circuit; draw it in a way which corresponds best with its Verilog description.)

module DrawMe(input a, b, c, output e);

assign e = (a & b) | !(b & c);

endmodule

Question 5 (8+6+2+2 marks)

The following circuit is a double flip-flop synchroniser. Note though that there is a 2 ns clock skew.

a) Each flip-flop has associated with it four values characterising it. What are the names of these four values? (Two end in“time”and two end in“delay”.)

b) In lectures, we drew a diagram involving blue, green and purple blocks, and used that diagram to derive conditions for such a circuit to function correctly. Draw such a diagram for the above circuit. Carefully indicate the start and finish times of each block. (You do not need to colour the blocks!    And you do not need to draw any“green”blocks because there is no combinational logic.)

c) Assume both flip-flops have identical characteristics. Write down a mathematical condition which must be met if this circuit is to perform correctly at very slow clock frequencies. (All values related to time will be assumed to be in nanoseconds.)

d) Write down a formula that the clock period must satisfy if the circuit is to function correctly. (All values related to time will be assumed to be in nanoseconds.)

Question 6.1 (7 marks)

Draw a circuit diagram, using only FETs, of a (2-input) NAND gate. Clearly distinguish n-channel and p-channel FETs (using the normal circuit symbols for them). Also label the gate, source and drain of each FET.

Question 6.2 (2 marks)

Draw a CMOS inverter (using only FETs).

Question 6.3 (2 marks)

Draw a CMOS AND gate (using only FETs).

Question 6.4 (7 marks)

Draw the input-output relationship of an ideal inverter. Assume 0 V represents logic“0”and 5 V represents logic“1”. Be as detailed as possible, including labelling the axes appropriately.

Question 7 (14 marks)

Write down 4-bit Grey code in order. (Hint: the first two lines should be 0000 then 0001.)

Question 8 (1+1+1+1+1+1 marks)

a) What is the binary representation of the smallest (most negative) 6-bit 2’s complement number?

b) What is the decimal representation of your answer to part (a)?

c) What is the binary representation of the largest (most positive) 6-bit 2’s complement number?

d) What is the decimal representation of your answer to part (c)?

e) What is the decimal representation of the 2’s complement number 5’sb01010?

f) What is the decimal representation of the 2’s complement number 5’sb10101?

Question 9 (1+2+1+1+1+1+1)

a) Is there a clock inside an FPGA? (Just answer“yes”or“no”.)

b) Inside a Logic Element are two main components, one used for implementing combinational logic and one used for implementing synchronous logic. What are these two main components?

c) Can the layout of your design (which logic elements are connected to which logic elements) significantly influence Fmax of your design? (Just answer“yes”or“no”.)

d) To increase Fmax, should you place your FPGA in a cold place or a hot place? (Just answer“cold” or“hot”.)

e) Can a logic element be connected directly to an FPGA pin? (Just answer“yes”or“no”.)

f) Does a CPU execute machine code? (Just answer“yes”or“no”.)

g) Does an FPGA execute Verilog code? (Just answer“yes”or“no”.)

Question 10 (1+2+1+1+1 marks)

a) A flip-flop’s supply voltage is 3.3 volts. If it becomes metastable, what is its output voltage?

b) Assume there is a 40% chance that a flip-flop recovers from metastability within 2 ns. What is the chance it will recover within 4 ns?

c) In a double flip-flop synchroniser, and approximately speaking, within how many clock cycles must a flip-flop recover from metastability for the synchroniser to function normally?

d) When must you use some type of synchroniser? (Only a short answer is required.)

e) Generally speaking, can you use parallel double flip-flop synchronisers to synchronise multiple bits? (Just answer“yes”or“no”.)

Question 11.1 (8 marks)

I have built a sensor. Every second, it will transmit an 8-bit number that is different from the            previously transmitted number. (Transmitting 9,8,9,8 is ok, but transmitting 9,9,8,8 is not allowed.) It will take at most 1 ms for the sensor to change numbers, therefore, for 999 ms out of 1,000 ms = 1   second, the number being transmitted will be correct and stable (it will not change).

On your DE1-SoC board, that you are using to receive this stream of 8-bit numbers, you have first put each bit through a double flip-flop synchroniser. This“synchronised input”will be denoted by “sync_in”.

Write a Verilog module with a 1-bit output that is a 1 whenever it has detected that sync_in has changed. Declare your module exactly like this:

module DetectChange(input clk, input [7:0] sync_in, output changed);

(Note“changed”is not a“reg”.)

Question 11.2 (9 marks)

Draw the state diagram for the following Moore FSM.

The input is 1-bit, called“changed”.

The output is 1-bit, called“sample_now”.

“sample_now”will be a 1, for a single clock cycle only, after it detects the input sequence 10000      (that is, a one followed by 4 zeros). After detecting 10000, it goes back to outputting zero, waiting for the next 10000.

Label the states any way you like (that is sensible), but use only six states. Indicate which is the starting state.

Question 11.3 (10 marks)

We want to implement in Verilog the FSM in Question 11.2. However, we want to wait until we have detected ten zeros, not four zeros, after a 1. Therefore, we want to implement the FSM                   algorithmically; we do not want to label by hand all the states.

The state will be represented by two registers.

reg last; // Holds the last input

reg [3:0] cnt; // Counts the number of zeros after a 1

Hints: cnt is normally 0. It only starts counting if“last == 1”and“changed == 0”. (Recall that         “changed”is the input to the FSM.) It will keep counting provided“last == 0”,“changed == 0”and “cnt > 0”.

a) Write down the output logic by completing the following statement.

assign sample_now =

b) Assume“next_last”and“next_cnt”have been appropriately declared. Complete the following transition logic.

always @(*) begin

next_last =

if (changed == 1) next_cnt =

else if (last == 1) next_cnt =

else if (cnt > 0) next_cnt =

end

Question 11.4 (10 marks)

From the answers to Questions 11.1 and 11.3 we have the following two modules. module DetectChange(input clk, input [7:0] sync_in, output changed);

module DetectStable(input clk, input changed, output sample_now);

Write a module that samples sync_in exactly when sample_now is a 1. The module’s output is this sampled version of sync_in. Use the DetectChange and DetectStable modules.

Declare your module exactly as follows.

module MySynchroniser(input clk, input [7:0] sync_in, output [7:0] received_data);