ELEC2141 – DIGITAL CIRCUIT DESIGN MID-TERM EXAMINATION TERM 1, 2019
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ELEC2141 – DIGITAL CIRCUIT DESIGN
MID-TERM EXAMINATION
TERM 1, 2019
Question 1 (50 marks)
a) Consider the following Boolean function F:
(, , , ) = ̅ + ̅ + + ̅
Assuming that the function is implemented using basic logic gates (NOT, AND and OR gates),
i. Find the total gate input-cost of the implementation. [3 marks]
ii. Express the function F as a sum-of-minterms (you may use the “little m” short cut notation). [4 marks]
iii. Simplify the function F using a Karnaugh map and express it as the sum-of-products. List all prime implicants and essential prime implicants. [8 marks]
iv. Express the function F as a product-of-sums. List all prime implicants and essential prime implicants. [8 marks]
v. For your design in part (iii), find the reduction in the total gate-input cost as compared to part (i). [3 marks]
b) Using a 4-to- 16 decoder, a 4-to- 1 multiplexer and any additional logic required, design a circuit that compares two 2-bit input binary numbers, = 10 and = 10 , and
produces an output with the result. Two input lines 1, 0 are used to select which of the four comparison functions from below appear at the output :
EQ = 1 when and are equal
GT = 1 when is greater than
LE = 1 when is less than
NULL = 0
Draw the full circuit. Clearly state any assumptions [15 marks].
c) Assuming that the and Clock inputs shown in the diagram below are applied to the circuit below, draw the waveforms for , and . [9 marks]
Question 2 (50 marks)
a) Convert octal 453.25 to base-7 and binary. Limit the number of digits in the fraction part to four. Show all your workings. [16 marks]
b) For the circuit below:
i. Write the Boolean function for the output F. [4 marks]
ii. Use algebraic simplification to optimise the function to its minimal form. [7 marks]
iii. Implement the optimised Boolean function using 2, 3 or 4 input NOR only gates. Do not assume that complements are available. [8 marks]
c) The truth table for the a 1-bit subtractor computing = − , with (borrow to the left) is shown below
A |
B |
D |
BL |
0 |
0 |
0 |
0 |
0 |
1 |
1 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
i. Design a 1-bit combinational subtractor with two data inputs (, ), a borrow from the right input (), a borrow request to the left output () and difference output
using only XOR, AND and inverter logic gates. [10 marks]
ii. Show how you would cascade your design to form a 4-bit subtractor. [5 marks]
2022-03-10