This assignment contributes 5% towards your final mark. It is to be completed individually, not in groups. Total Marks: 100.

This assignment is due before the start of your next lab session, i.e. before the start of the Week 2   lab session for Thurs/Fri labs, and before the start of the Week 3 lab session for Monday labs. Late assignments will be subjected to the University’s late submission policy unless accompanied by a valid   special consideration form. Plagiarism will be dealt within accordance with the University of Sydney     plagiarism policy. Lab submissions will not be accepted more than a week after the due date.

Assignments will be assessed based on the following components. Incomplete submissions will have severely reduced marks:

●   Report: Submit a .pdf report using the class Canvas site. The report can be very simple, and needs only directly address the questions laid out in the assignment.

The cover page for your report should include your SID and tutorial section, but do not include your name to comply with the University’s anonymous marking policy.

Code appendix: The appendix of your report must contain a printout (in text format) of all source code written for the assignment. File header comments and proper formatting will be critical to making this section readable.

Code: Submit your code (code only, no binaries) in a .zip file via the canvas site.

You may find libreoffice writer or google or microsoft’s online tools useful for preparing your report. For printing out and appending code to your report, you can use:

find . -name "*.cpp" -o -name "*.h" | xargs enscript --color=1 -C -Ecpp

-fCourier8 -o - | ps2pdf - code.pdf

pdfunite <report name>.pdf code.pdf <concatenated report name>.pdf

The first command recursively finds  .cpp and .h files and formats them as a pdf called code.pdf. The second command concatenates the code to an existing pdf file.

Combinatorial Logic Simulator

You have been provided with an object-oriented implementation of a combinatorial logic simulator. Read the provided A1.LogicSim.v0.cpp including the details laid out in the header comment. Compile, run,    and understand this implementation.

Understanding the Provided Code

The code provided has some important limitations, but it works. Without changing the code’s structure or behaviour, answer the following briefly in your report:

[5 marks] Draw the logic circuit that the provided code simulates. Include labels for the wires and gates. [5 marks] Write down the sequence of class interactions that occurs when the first call of DriveLevel  occurs in main. This should be a bulleted list in which each bullet corresponds to an interaction between   functions or classes.

An example class interaction sequence from a different project:

●   main calls CKitchen.OvenIsHot

●   CKitchen.OvenIsHot calls mRobot.GetThePizza, passing it an OvenID

●    … morefunction calls

●   CRobot.GetThePizza returns program flow to CKitchen.OvenIsHot

●   CKitchen.OvenIsHot returns program flow to main

Hints:

●   You may wish to instrument the code without changing its structure or behaviour by adding console output (std::cout) throughout.

Redesigning the Program

While parts of the provided code are well-designed and well-written, some rules of object-oriented design are broken, in particular the contents of main are not well encapsulated in objects. There are also

examples of poor coding style including a lack of comments throughout. Redesign and refactor the code following the principles of object oriented design and coding best-practices discussed in lectures.

Simplifications:

●   The code has the limitations that only NAND gates are supported, and the circuit topology is hard-coded. You should NOT address these limitations for this exercise.

●   Because this is a small example, you may place your entire program in one C++ file.

Hints:

●   The nand gate and wire classes are pretty well structured.

●   When choosing classes to add, think about mirroring a physically meaningful setup. What are the objects that we discuss when testing combinatorial logic circuits? Is the part that generates test     signals the same as the part that’s being tested? Your design should exhibit meaningful objects

and relationships between objects.

Testing the Program

Implement an OR function using your refactored code.

Hints:

●   This should be built out of NAND gates, do not introduce a new OR gate class

●   The syntax for adding gates and wires should closely resemble that used in the original program.

[ 10 Marks] Functionality: In your report copy/paste the output from your program running an OR gate. Do not use screenshots, and do not include additional debugging / logging outputs. The output should     resemble a simple truth table, like the output of the originally provided code. The report and the code in  your attached .zip file will be assessed for correct functionality.

[30 Marks] Code Quality: Your code will be assessed based on style and coding best practices as taught in lecture. The teaching staff will comment on the code in your report’s appendix, and so it is important     that this be included in your pdf as text and not screenshots.

[50 Marks] Design: In your report list the classes in your design and the data and methods each class will   contain, using a table format similar to the ones seen in the Practice Question P5. This table and your code will be assessed based on appropriate use of the design principles taught in lecture.