EEE201 CMOS Digital Integrated Circuits (2022-2023)
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Homework 1 on Electronic Devices in Silicon CMOS ICs
in the module
EEE201 CMOS Digital Integrated Circuits
1. In the MOS transistors of a digital integrated circuits (ICs), the drain diffusion region has an n- type doping of 1018 cm-3 on a silicon substrate with the p-type doping of 1016 cm-3 .
Image from: Donald A. Neamen, Microelectronics: Circuit Analysis & Design, 4th edition, © 2010 McGraw-Hill, USA.
(a). What is the approximate intrinsic carrier concentration in silicon at room temperature (T = 300 K)? Hence or otherwise, calculate the built-in potential Vbi of the p-n junction between the p-type substrate and the n-type drain region at room temperature.
(b). Using the result in (a) or otherwise, calculate the depletion width of the p-n junction when both the drain and the substrate are not connected to any voltage.
(c). Using Matlab or Excel, plot a graph of the depletion width when the substrate is connected to ground and the drain voltage VDS varies from +3.0 V to 0 V.
(d). If the drain diffusion regions have a total area of 40 µm × 0.6 µm, using the result in (b) or otherwise, calculate the depletion capacitance of the drain terminal in the open-circuit condition. Assume the sidewall contribution to the depletion capacitance to be negligible.
(e). If the depth of the drain diffusion region is 0.15 µm, calculate the sidewall contribution to the depletion capacitance in the open-circuit condition (i.e. zero-biased).
(f). Using Matlab or Excel, plot a graph of the total depletion capacitance (with the sidewall contribution included) when the substrate is connected to ground and the drain voltage VDS varies from +3.0 V to 0 V.
Assume an abrupt junction (i.e. abrupt metallurgical boundary in the p-n junction) in all the calculations. Please find out the physical constants (e.g. Boltzmann’s constant kB) from textbooks or reliable websites on the internet.
2. MOS transistors of the same digital integrated circuits (ICs) described in Question 1 have a gate oxide thickness tox of 30 Å (i.e. 3.0 nm) and an effective channel length L = 0.15 µm and channel width W = 40 µm.
(a). Calculate the normalised gate oxide capacitance Cox of the MOS transistors. Assume the gate oxide is made of high quality silicon dioxide (SiO2).
(b). Determine the gate-to-source capacitance CGS of the MOS transistor operating in the saturation region.
(c). Determine the gate-to-drain capacitance CGD of the MOS transistor if it operates in the linear region. How does the value of CGD compare with the depletion capacitance of the drain-to-substrate junction?
(d). It is given the electron mobility for the MOS transistors is 370 cm2/Vs and the threshold voltage VT of the n-channel MOS transistors is 0.45 V. Assuming the long-channel approximation, using Matlab or Excel, plot a graph of the output characteristics (i.e. IDS vs. VDS) of a MOS transistor with a channel width W = 40 µm and L = 0.15 µm for VGS = 0.7 V, 1.0 V, 1.5 V and 2.0 V while VDS varies from 0 V to 2.5 V.
(e). With the same parameters and the long-channel approximation, using Matlab or Excel, plot a graph of the transfer characteristics (i.e. IDS vs. VGS) of a MOS transistor of the same size W/L = 40 µm/0.15 µm for VDS = 0.2 V, 1.0 V, 2.0 V while VGS varies from 0 V to 2.0 V. Assume the current is zero when VGS is below the threshold voltage VT .
(f). If hafnium oxide (HfO2) with a dielectric constant of 25 is used to replace the silicon dioxide (SiO2) as the gate dielectric, what would be the gate oxide thickness tHfO to keep same the normalised gate oxide capacitance Cox as that obtained in Q2(a)?
Note: In all the calculations, please show your steps clearly. When you find the values of some material parameters or physical constants (not provided in the questions), please cite the source(s) explicitly as a footnote or include a section of references at the end.
2022-11-04